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Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DESCRIPTION
Monolithic temperature and overload protected logic level power MOSFET in a 3 pin plastic envelope, intended as a general purpose switch for automotive systems and other applications.
BUK101-50DL
QUICK REFERENCE DATA
SYMBOL VDS ID PD Tj RDS(ON) IISL PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance Input supply current VIS = 5 V MAX. 50 26 75 150 60 650 UNIT V A W C m A
APPLICATIONS
General controller for driving lamps motors solenoids heaters
FEATURES
Vertical power DMOS output stage Low on-state resistance Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by input 5 V logic compatible input level Control of power MOSFET and supply of overload protection circuits derived from input Lower operating input current permits direct drive by micro-controller ESD protection on input pin Overvoltage clamping for turn off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
DRAIN
O/V CLAMP INPUT
RIG
POWER MOSFET
LOGIC AND PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - TO220AB
PIN 1 2 3 tab input drain source drain DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
D TOPFET I
P
1 23
S
April 1993
1
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDS VIS ID ID IDRM PD Tstg Tj Tsold PARAMETER Continuous drain source voltage Continuous input voltage Continuous drain current Continuous drain current Repetitive peak on-state drain current Total power dissipation Storage temperature Continuous junction temperature2 Lead temperature
1
BUK101-50DL
CONDITIONS Tmb 25 C; VIS = 5 V Tmb 100 C; VIS = 5 V Tmb 25 C; VIS = 5 V Tmb 25 C normal operation during soldering
MIN. 0 -55 -
MAX. 50 6 26 16 100 75 150 150 250
UNIT V V A A A W C C C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload. SYMBOL VISP VDDP(T) VDDP(P) PDSM PARAMETER Protection supply voltage
3
CONDITIONS for valid protection
MIN. 4
MAX. -
UNIT V
Over temperature protection Protected drain source supply voltage VIS = 5 V Short circuit load protection Protected drain source supply voltage5 VIS = 5 V Instantaneous overload dissipation Tmb = 25 C
4
-
50 20 1.3
V V kW
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL IDROM EDSM EDRM PARAMETER Repetitive peak clamping current Non-repetitive clamping energy Repetitive clamping energy CONDITIONS VIS = 0 V Tmb 25 C; IDM = 26 A; VDD 20 V; inductive load Tmb 95 C; IDM = 8 A; VDD 20 V; f = 250 Hz MIN. MAX. 26 625 40 UNIT A mJ mJ
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 k MIN. MAX. 2 UNIT kV
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 The input voltage for which the overload protection circuits are functional. 4 For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS. 5 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDDP(P) maximum.
April 1993
2
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
THERMAL CHARACTERISTICS
SYMBOL PARAMETER Thermal resistance Rth j-mb Rth j-a Junction to mounting base Junction to ambient in free air CONDITIONS MIN.
BUK101-50DL
TYP.
MAX.
UNIT
1.3 60
1.67 -
K/W K/W
STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL V(CL)DSS V(CL)DSS IDSS IDSS IDSS RDS(ON) PARAMETER Drain-source clamping voltage Drain-source clamping voltage CONDITIONS VIS = 0 V; ID = 10 mA MIN. 50 TYP. 0.5 1 10 45 MAX. 70 10 20 100 60 UNIT V V A A A m
VIS = 0 V; IDM = 2 A; tp 300 s; 0.01 Zero input voltage drain current VDS = 12 V; VIS = 0 V Zero input voltage drain current VDS = 50 V; VIS = 0 V Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 C Drain-source on-state VIS = 5 V; IDM = 13 A; tp 300 s; resistance1 0.01
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input. SYMBOL EDS(TO) td sc ID(SC) IDM(SC) Tj(TO) PARAMETER Short circuit load protection Overload threshold energy Response time Drain current3 Peak drain current4
2
CONDITIONS Tmb = 25 C; L 10 H; RL = 10 m VDD = 13 V; VIS = 5 V VDD = 13 V; VIS = 5 V VDD = 13 V; VIS = 5 V VIS = 5 V; VDD = 13 V
MIN. 150
TYP. 0.4 0.8 45 105 -
MAX. -
UNIT J ms A A C
Over temperature protection Threshold junction temperature VIS = 5 V; from ID 1 A5
TRANSFER CHARACTERISTIC
Tmb = 25 C SYMBOL gfs PARAMETER Forward transconductance CONDITIONS VDS = 10 V; IDM = 13 A tp 300 s; 0.01 MIN. 10 TYP. 16 MAX. UNIT S
1 Continuous input voltage. The specified pulse width is for the drain current. 2 Refer to OVERLOAD PROTECTION LIMITING VALUES. 3 Continuous drain-source supply voltage. Pulsed input voltage. 4 Continuous input voltage. Momentary short circuit load connection. (The higher peak current is due to the effect of capacitance Cgd). 5 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition.
April 1993
3
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
INPUT CHARACTERISTICS
BUK101-50DL
Tmb = 25 C unless otherwise specified. The supply for the logic and overload protection is taken from the input. SYMBOL VIS(TO) IIS VISR IISL V(BR)IS RIG PARAMETER Input threshold voltage Input supply current Protection reset voltage1 Input supply current Input breakdown voltage Input series resistance to gate of power MOSFET protection latched; II = 10 mA Tj = 25 C Tj = 150 C CONDITIONS VDS = 5 V; ID = 1 mA normal operation; VIS = 5 V VIS = 4 V Tj = 25 C Tj = 150 C VIS = 5 V VIS = 3.5 V MIN. 1.0 100 2.0 1.0 6 TYP. 1.5 200 160 2.6 330 240 33 50 MAX. 2.0 350 270 3.5 650 430 UNIT V A A V A A V k k
SWITCHING CHARACTERISTICS
Tmb = 25 C. RI = 50 . Refer to waveform figure and test circuit. SYMBOL td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time CONDITIONS VDD = 13 V; VIS = 5 V resistive load RL = 2.1 VDD = 13 V; VIS = 0 V resistive load RL = 2.1 MIN. TYP. 17 75 60 70 MAX. UNIT s s s s
REVERSE DIODE LIMITING VALUE
SYMBOL IS PARAMETER Continuous forward current CONDITIONS Tmb 25 C; VIS = 0 V MIN. MAX. 26 UNIT A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 C SYMBOL VSDO trr PARAMETER Forward voltage Reverse recovery time CONDITIONS IS = 26 A; VIS = 0 V; tp = 300 s not applicable
2
MIN. -
TYP. 1.0 -
MAX. 1.5 -
UNIT V -
1 The input voltage below which the overload protection circuits will be reset. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
April 1993
4
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
ENVELOPE CHARACTERISTICS
SYMBOL Ld Ld Ls PARAMETER Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad MIN. -
BUK101-50DL
TYP. 3.5 4.5 7.5
MAX. -
UNIT nH nH nH
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1000
ID & IDM / A Overload protection characteristics not shown
BUK101-50DL
100
RD S( O
= N)
VD
S/I
D
tp = 100 us
10 1 ms DC 10 ms 100 ms
0
20
40
60
80 100 Tmb / C
120
140
1 1 10 VDS / V 100
Fig.2. Normalised power dissipation. PD% = 100PD/PD(25 C) = f(Tmb)
Normalised Current Derating
Fig.4. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth / (K/W) BUK101-50DL
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
10
D= 1 0.5 0.2 0.1 0.1 0.05 0.02 0 1E-05 1E-03 t/s
P D tp D= tp T t
0
20
40
60
80 Tmb / C
100
120
140
0.01 1E-07
T
1E-01
1E+01
Fig.3. Normalised continuous drain current. ID% = 100ID/ID(25 C) = f(Tmb); conditions: VIS = 5 V
Fig.5. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
April 1993
5
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK101-50DL
50
ID / A VIS / V =
BUK101-50DL 6 5.5 5 4.5 4
100
td sc / ms
BUK101-50DL
40
10
30
20 3.5 10 3
PDSM 1
0 0 1 2 VDS / V 3 4 5
0.1 0.1 1 PDS / kW 10
Fig.6. Typical on-state characteristics, Tj = 25 C. ID = f(VDS); parameter VIS; tp = 2 ms
RDS / mOhm VIS / V = 100 80 60 40 20 0 0 20 ID / A 40 3.5 4.5 4 5 5.5 6 BUK101-50DL
Fig.9. Typical overload protection characteristics. td sc = f(PDS); conditions: VIS 4 V; Tj = 25 C.
PDSM% 120 100 80 60 40 20 0 -60 -40 -20 0 20 40 60 Tmb / C 80 100 120 140
120
Fig.7. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VIS; tp = 2 ms
a
Fig.10. Normalised limiting overload dissipation. PDSM% =100PDSM/PDSM(25 C) = f(Tmb)
Energy & Time BUK101-50DL
Normalised RDS(ON) = f(Tj)
1
1.5
Time / ms
1.0
0.5
0.5
Energy / J Tj(TO)
0
-60 -40 -20
0
20
40 60 Tj / C
80
100 120 140
0 -60 -20 20 60 100 Tmb / C 140 180 220
Fig.8. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 13 A; VIS = 5 V
Fig.11. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 m
April 1993
6
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK101-50DL
30
ID / A
BUK101-50DL
100
IS / A
BUK101-50DL
20 typ.
50
10
0 50 60 VIS / V 70
0 0 1 VSD / V 2
Fig.12. Typical clamping characteristics, 25 C. ID = f(VDS); conditions: VIS = 0 V; tp 50 s
VIS(TO) / V
Fig.15. Typical reverse diode current, Tj = 25 C. IS = f(VSDS); conditions: VIS = 0 V
VDD
2 max.
RL
typ.
1
min.
TOPFET I
P
D
D.U.T. S ID measure 0V 0R1
RI VIS
0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140
Fig.13. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IISL & IIS / uA BUK101-50DL
Fig.16. Test circuit for resistive load switching times.
600 500 400
15
VIS / V & VDS / V
BUK101-50DL
PROTECTION LATCHED
VDS 10
IISL 300 200 100 0 0 2 VIS / V 4 6
0 200 400 time / us 600
RESET IIS
VIS 5
NORMAL
0
Fig.14. Typical DC input characteristics, Tj = 25 C. IISL & IIS = f(VIS); protection latched & normal operation
Fig.17. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 ; RI = 50 , Tj = 25 C.
April 1993
7
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK101-50DL
120 110 100 90 80 70 60 50 40 30 20 10 0
EDSM%
1 mA
Idss
100 uA
10 uA
typ.
1 uA
100 nA 0 20 40 60 80 Tmb / C 100 120 140 0 20 40 60 80 Tj / C 100 120 140
Fig.18. Normalised clamping energy rating. EDSM% = f(Tmb); conditions: ID = 26 A; VIS = 5 V
V(CL)DSS VDS VDD 0 ID 0 VIS 0
D TOPFET I
Fig.20. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
Iiso & Iisl normalised to 25 C
+
L VDS
VDD
1.5
-ID/100 D.U.T.
1
P
Schottky
RIS
S
R 01 shunt
0.5 -60 -20 20
Fig.19. Clamping energy test circuit, RIS = 50 . 2 EDSM = 0.5 LID V(CL)DSS /(V(CL)DSS - VDD )
60 Tj / C
100
140
180
Fig.21. Normalised input currents (normal & latched). IISO/IISO25C & IISL/IISL25C = f(Tj); VIS = 5 V
April 1993
8
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
BUK101-50DL
4,5 max 10,3 max
1,3
3,7 2,8
5,9 min
15,8 max
3,0 max not tinned
3,0
13,5 min
1,3 max 1 2 3 (2x)
2,54 2,54
0,9 max (3x)
0,6 2,4
Fig.22. TO220AB; pin 2 connected to mounting base.
Notes 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8".
April 1993
9
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK101-50DL
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
April 1993
10
Rev 1.100

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